The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device with an adaptive output driver capable of varying its strength according to the variation in voltage and temperature.
An output driver plays a role as an interface between a DRAM and its external devices in a reading operation. Therefore, the DC and AC characteristics of the output driver must be stable with varying voltage, temperature and manufacturing processes. In particular, this stability is keenly required in high-speed operational devices. First of all, the DC characteristics, represented by IBIS (input/output buffer information specification), IOH (output high current), IOL (output low current) and so on, limit the impedance of the output driver to a given range over the entire voltage range. However, if there is no circuit to compensate the variation in manufacturing processes, voltage and temperature, it is difficult to limit the impedance of the output driver to the given range. Further, the AC characteristics of the output driver, such as slew rate or skew between data, vary according to manufacturing processes, voltage and temperature. These parameters have a great influence on a margin to the product specification as well as signal integrity.
In general, there are many types of output drivers; most noticeable are the tri-state CMOS output driver and the open drain output driver. Hereinafter, the former output driver will be described as an example.
FIG. 1A provides a schematic diagram of a conventional tri-state CMOS output driver and FIG. 1B shows a waveform diagram of the internal signals from a conventional output driver.
The output driver connected to a data pin consists of a PMOS transistor MP1 and an NMOS transistor MN1, which are constructed to share an input buffer and a pad. Gates of the PMOS transistor MP1 and the NMOS transistor MN1 are provided with an up signal UP and a down signal DN, respectively.
As shown in FIG. 1B, the up signal UP and the down signal DN output data with waveforms capable of maintaining high impedance at the pad.
Meanwhile, a reference voltage Vref having a voltage level of Vextq/2 is supplied from the outside of a DRAM. A serial termination resistor Rs and a parallel termination resistor Rt which are connected to the pad are attached to a termination voltage Vtt at the outside of the DRAM where the termination voltage Vtt has a voltage level of Vrefxc2x10.04 V and is supplied from the outside.
Since a data masking (DM) pin is only used in writing operations, there exists only an input buffer. However, a dummy output driver can be used for the DM pin to match data strobe and loading. The dummy output driver is made of a PMOS transistor MP2 and an NMOS transistor MN2. Gates of the PMOS and NMOS transistors MP2 and MN2 are connected to an external supply voltage Vextq and a ground voltage Vssq, respectively. Thus, the transistors MP2 and MN2 also play a role as diodes.
However, in the above structure, since the strength of the output driver is not variable with the variation in voltage and temperature, the output driver fails to control the variation of current and voltage thereof.
It is, therefore, a primary object of the present invention to provide a semiconductor memory device employing an adaptive output driver capable of varying its strength according to the variation in external voltage, temperature and so on.
In accordance with the present invention, there is provided a semiconductor memory device with an adaptive output driver, comprising: a control means for producing a control signal to control the voltage level of the adaptive output driver; data masking buffering means for generating a reference voltage to be compared with the voltage level of the adaptive output driver; the adaptive output driver whose strength varies in response to the control signal provided from the control means; and comparison means for comparing the reference voltage with the voltage level of the adaptive output driver to thereby generate a signal determining whether or not the control means should perform a shift operation.
The adaptive output driver includes a plurality of pull-up transistors for pull-up driving an output terminal of the semiconductor memory device in response to the control signal of the shift register unit and a control signal of a pre-driver. It also includes a plurality of pull-down transistors which are connected to the plurality of pull-up transistors in parallel, for pull-down driving the output terminal in response to the control signal of the shift register unit and the control signal of the pre-driver.
In the shift register unit, the plurality of pull-up transistors consist of 4 PMOS transistors, which are turned-on or turned-off in response to the control signal of the shift register unit. Among the 4 PMOS transistors, the number of transistors to be turned-off increases depending on the comparison result of the comparator.
In the shift register unit, the plurality of pull-down transistors consist of 4 NMOS transistors, which are turned-on or turned-off in response to the control signal of the shift register unit. Among the 4 NMOS transistors, the number of transistors to be turned-off increases depending on the comparison result of the comparator.
In the above, the shift register unit includes a pull-up shift register for receiving the signal generated from the comparator to thereby produce a control signal controlling the plurality of pull-up transistors, and a pull-down shift register for receiving the signal produced from the comparator to thereby generate a control signal controlling the plurality of pull-down transistors.
Further, the data masking buffer includes a PMOS transistor group made of a plurality of PMOS transistors serially connected to each other and an NMOS transistor group consisting of a multiplicity of NMOS transistors serially connected to each other, wherein the PMOS transistor group and the NMOS transistor group are attached to each other serially, vertically and symmetrically and a node connecting the PMOS transistor group and the NMOS transistor group is attached to a termination voltage Vtt node. The PMOS transistor group and the NMOS transistor group contain 3 PMOS transistors and 3 NMOS transistors, respectively. Meanwhile, among the PMOS transistor group, a resistor is connected between a gate and a drain of some PMOS transistors and among the NMOS transistor group, a resistor is attached between a gate and a drain of some NMOS transistors.
In accordance with the present invention, the strength of the output driver is changed with respect to the voltage and the temperature by employing a plurality of NMOS transistors and PMOS transistors in the output driver and controlling the number of transistor to be turned-on by using a register. Since the variation of the reference voltage Vrefn for the termination voltage Vtt according to the temperature variation of xe2x88x9210xc2x0 C. to 90xc2x0 C. is very small, it is possible to accurately control the temperature compensation in an operational range and vary the size of the output driver according to the variation of the temperature and the voltage. For example, if the external voltage becomes higher, the shift operation of the shift register is performed in the direction of decreasing overall strength by reducing the size of the output driver. On the other hand, if the external voltage becomes lower, the shift operation of the shift register is executed in the direction of increasing overall strength by increasing the size of the output driver.